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FUJITSU SEMICONDUCTOR DATA SHEET
DS05-13103-2E
Memory FRAM
CMOS
1 M Bit (128 K x 8)
MB85R1001
DESCRIPTIONS
The MB85R1001 is an FRAM (Ferroelectric Random Access Memory) chip in a configuration of 131,072 words x 8 bits, using the ferroelectric process and silicon gate CMOS process technologies for forming the nonvolatile memory cells. Unlike SRAM, MB85R1001 is able to retain data without back-up battery. The memory cells used for the MB85R1001 has improved at least 1010 times of read/write access, significantly outperforming FLASH memory and E2PROM in endurance. The MB85R1001 used a pseudo - SRAM interface compatible with conventional asynchronous SRAM.
FEATURES
* * * * * Bit configuration : 131,072 words x 8bits Read/write endurance : 1010 times Operating power supply voltage : 3.0 V to 3.6 V Operating temperature range : -20 C to +85 C 48-pin, TSOP (1) plastic package
PACKAGE
48-pin plastic TSOP(1)
(FPT-48P-M25)
MB85R1001
PIN ASSIGNMENTS
(TOP VIEW)
A11 A9 N.C. A8 A13 WE CE2 A15 N.C. VCC N.C. N.C. GND N.C. N.C. VCC N.C. A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 OE N.C. GND A10 CE1 N.C. I/O8 I/O7 I/O6 I/O5 I/O4 VCC N.C. I/O3 I/O2 I/O1 N.C. N.C. N.C. A0 A1 GND A2 A3
(FPT-48P-M25)
PIN DESCRIPTIONS
Pin name A0 to A16 I/O1 to I/O8 CE1 CE2 WE OE VCC GND Address In Data Input/Output Chip Enable 1 in Chip Enable 2 in Write Enable in Output Enable in Power Supply Ground Function
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MB85R1001
BLOCK DIAGRAM
A0 to * * * Address Latch. Row Dec. Ferro Capacitor Cell
A16 Column Dec. intCE2 S/A CE2 intCEB WE OE I/O8 CE1 intCEB * * to I/O1 intCE2 intOE intWE intCE2 I/O1 to I/O8
FUNCTION TRUTH TABLE
Operation Mode Standby Pre-charge CE1 H X X Read Read (Pseudo SRAM, OE control) Write L Write (Pseudo SRAM, WE control) Output Disable L L H H H H H High-Z L L H H CE2 X L X H WE X X H H H L H Din Operation (ICC) OE X X H L Dout High-Z Standby (ISB) I/O1 to I/O8 Supply Current
L = VIL, H = VIH, X can be either VIL or VIH, High-Z = High Impedance : Latch address at falling edge, : Latch address at rising edge 3
MB85R1001
ABSOLUTE MAXIMUM RATINGS
Parameter Supply Voltage Input Voltage Output Voltage Ambient Temperature Storage Temperature Symbol VCC VIN VOUT TA Tstg Rating Min -0.5 -0.5 -0.5 -20 -40 Max +4.0 VCC+0.5 VCC+0.5 +85 +125 Unit V V V C C
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
RECOMMENDED OPERATING CONDITIONS
(VCC = 3.0 V to 3.6 V, TA = -20 C to +85 C) Value Unit Typ Max 3.3 3.6 VCC + 0.5 0.8 +85 V V V C
Parameter Supply Voltage Input Voltage (high) Input Voltage (low) Operating Temperature
Symbol VCC VIH VIL TA
Min 3.0 VCC x 0.8 -0.5 -20
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
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MB85R1001
ELECTRICAL CHARACTERISTICS
1. DC CHARACTERISTICS
Parameter Input Leakage Current Output Leakage Current Supply Current Symbol |ILI| |ILO| ICC Test Condition VIN = 0 V to VCC VOUT = 0 V to VCC, CE1 = VIH or OE = VIH CE1 = 0.2 V, CE2 = VCC-0.2 V, Iout = 0 mA*1 CE1 VCC-0.2 V Standby Current Output Voltage (high) Output Voltage (low) *1 : Iout : Output current *2 : All other inputs (CE1, CE2, OE, WE) should be at CMOS levels, i.e., H VCC - 0.2 V, L 0.2 V. ISB VOH VOL CE2 0.2 V*2 OE VCC-0.2 V, WE VCC-0.2 V*2 IOH = -2.0 mA IOL = 2.0 mA 0.8 x VCC 0.4 V V 10 100 A (VCC = 3.0 V to 3.6 V, TA = -20 C to +85 C) Value Unit Min Typ Max 10 10 10 A A mA
5
MB85R1001
2. AC CHARACTERISTICS
* AC TEST CONDITIONS Supply Voltage Operating Temperature Input Voltage Amplitude Input Rising Time Input Falling Time Input Evaluation Level Output Evaluation Level Output Impedance (1) Read Operation (VCC = 3.0 V to 3.6 V, TA = -20 C to +85 C) Parameter Read Cycle Time CE1 Active Time OE Active Time Pre-charge Time Address Setup Time Address Hold Time OE Setup Time CE1 Access Time CE2 Access Time OE Access Time OE Output Floating Time (2) Write Operation (VCC = 3.0 V to 3.6 V, TA = -20 C to +85 C) Parameter Write Cycle Time CE1 Active Time CE2 Active Time Pre-charge Time Address Setup Time Address Hold Time Write Pulse Width Data Setup Time Data Hold Time Write Setup Time Symbol tWC tCA1 tCA2 tPC tAS tAH tWP tDS tDH tWS Value Min 250 210 210 40 10 50 210 10 50 0 Max 2,000 2,000 Unit ns ns ns ns ns ns ns ns ns ns Symbol tRC tCA1 tRP tPC tAS tAH tES tCE1 tCE2 tOE tOHZ Value Min 250 210 210 40 10 50 10 Max 2,000 2,000 100 100 100 25 Unit ns ns ns ns ns ns ns ns ns ns ns : 3.0 V to 3.6 V : -20 C to +85 C : 0.3 V to 2.7 V : 10 ns : 10 ns : 2.0 V / 0.8 V : 2.0 V / 0.8 V : 50 pF
6
MB85R1001
(3) Power ON/OFF Sequence Parameter CE1 LEVEL holding time in Power OFF CE1 LEVEL holding time in Power ON Power interval * * : Condition for power detection circuit to function Symbol tpd tpu tpi Value Min 85 85 0.5 Typ Max Units ns ns s
3. Pin Capacitance
(f = 1 MHz, TA = +25 C) Parameter Input Capacitance Output Capacitance Symbol CIN COUT Test Condition VIN = GND VOUT = GND Value Min Typ Max 10 10 Unit pF pF
4. Reliability
Data retention 10 years (TA = 0 C to +55 C) Access endurance 1010 times (TA = -20 C to +85 C)
7
MB85R1001
TIMING DIAGRAMS
1. Read Cycle Timing
* CE1, CE2 Control
tRC tCA1 tCE1 CE1 tPC
CE2 tAS A0 to A16 Valid tES OE tAH
tCE2
tRP tOE tOHZ High-Z Valid
I/O1 to I/O8
* OE Control
tRC
tCA1 CE1 tPC
CE2 tAS A0 to A16 Valid tAH
tCA2
tRP OE tOE I/O1 to I/O8 Valid tOHZ High-Z
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MB85R1001
2. Write Cycle Timing
* CE1, CE2 Control
tWC tCA1 CE1 tPC
CE2 tAS A0 to A16 Valid tWS WE tAH
tCA2
tWP
OE tDS Data In tDH
Valid
* WE Control
tWC tCA1 CE1 tPC
CE2
tCA2
tAS A0 to A16 Valid
tAH
WE
tWP
OE tDS Data In tDH
Valid
9
MB85R1001
POWER ON/OFF SEQUENCE
tpd tpi tpu
VCC CE2 3.0 V
VIH (Min)
VCC CE2 3.0 V
VIH (Min)
1.0 V
1.0 V
VIL (Max)
VIL (Max)
CE2 0.2 V
GND GND
CE1 > VCC x 0.8*
CE1 : Don't Care
CE1 > VCC x 0.8*
CE1 * : CE1 (Max) < VCC + 0.5 V
CE1
NOTES ON USE
After IR reflow, the hold of data that was written before IR reflow is not guaranteed.
ORDERING INFOMATION
Part number MB85R1001PFTN Package 48-pin plastic TSOP(1) (FPT-48P-M25) Remarks
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MB85R1001
PACKAGE DIMENTION
48-pin plastic TSOP(1) (FPT-48P-M25) Note 1) *1 : Resin protrusion. (Each side : +0.15 (.006) Max). Note 2) *2 : These dimensions do not include resin protrusion. Note 3) Pins width and pins thickness include plating thickness. Note 4) Pins width do not include tie bar cutting remainder.
0.100.05 (Stand off) (.004.002) LEAD No.
1 48
INDEX
0.50(.020)
0.22 -0.04
*1 12.000.10 (.472.004)
+0.05 +.002
.009 -.002
0.10(.004)
M
24
25
14.000.20(.551.008)
*2 12.400.10(.488.004)
1.130.07 (Mounting height) (.044.003) Details of "A" part "A" 0~8
+0.05 +.002
0.08(.003)
0.145 -0.03 .006 -.001
0.25(.010)
0.600.15 (.024.006)
C
2003 FUJITSU LIMITED F48043S-c-2-2
Dimensions in mm (inches). Note: The values in parentheses are reference values.
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MB85R1001
FUJITSU LIMITED
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party's intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.
F0501 (c) 2005 FUJITSU LIMITED Printed in Japan

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